This invention relates generally to differential amplifiers and in particular to a differential amplifier having a feedback circuit for stabilizing its common mode operating point and for tracking input threshold variations in digital logic circuits.
Gallium arsenide (GaAs) technology is advancing rapidly in research laboratories but has been slow to gain acceptance in commercial applications. Two factors contribute to the reluctance of system designers to incorporate GaAs components in their products: difficulties of interfacing GaAs components with the silicon bipolar circuitry presently in widespread use, and the limited range of integrated circuit components presently available in GaAs.
The difficulties of interfacing GaAs components with silicon bipolar circuitry stem from the different logic voltage levels required by the different integrated circuit families. Emitter Coupled Logic (ECL), for example, is a high-speed bipolar technology which typically operates at a reference, or common mode level, of -1.29 or -1.33 volts and has output swings of 500 millivolts above and below this level. Three-Diode Buffered FET Logic (BFL), one of the GaAs logic families, operates at a reference level of -0.5 volts and has output swings of 1 volt above and below this level.
The translation of logic signals from one such logic family to the other is complicated by the different temperature-response characteristics of the two materials. The reverse saturation current of a silicon diode junction, for example, doubles for every 10.degree. C. rise in temperature. The forward voltage drop across a silicon junction drops 20 millivolts over the same range. Compensation for these temperature related effects is comparatively easy in a wholly silicon based system, since all the circuitry behaves similarly. When a GaAs circuit is interfaced through a translator circuit with a silicon circuit, however, the temperature drift of the silicon generated logic levels will not match the temperature drift of the GaAs logic levels. The translated silicon levels can thus drift away from the desired GaAs levels, causing the system performance to become marginal. Accordingly, proper temperature stabilization of silicon to GaAs translator circuits is an obstacle that must be overcome before GaAs components can enjoy widespread commercial acceptance.
The second factor slowing commercial acceptance of GaAs technology is the limited range of GaAs integrated circuits presently available. This limited range of components can be traced, in part, to the inherent difficulties of implementing certain circuit topologies satisfactorily in GaAs. Differential amplifiers, for example, have been widely used in the silicon integrated circuitry art as building blocks in components such as latches, shift registers and digital-to-analog converters. Optimization of such circuits in GaAs, however, is made difficult by the many problems inherent in GaAs technology which are not present with silicon. Some of these problems include: the inherently low gain of GaAs transistors, the difficulties of fabricating large value resistors and high impedance current sources, the poor matching of adjacent GaAs components, the wide process variations in the pinch-off voltage of GaAs field effect transistors (GaAsFETs) and the dependence of GaAsFET drain currents on drain to source voltages. Such factors make any symmetrical circuit topology, such as the differential amplifier, difficult to implement in GaAs. Consequently, GaAs circuits which rely on symmetrical topologies, such as logic families that use phase matched differential inputs or outputs, are unavailable.
In response to the interfacing problem, many designers have proposed circuits for translating bipolar ECL logic signals to gallium arsenide compatible levels. An input translator circuit is discussed in the "IEEE Journal of Solid State Circuits", Vol. SC-19, No. 1, February 1984, page 10. This circuit uses a reference voltage which is set by the ratio of the component GaAsFET gate widths. Such a scheme is highly dependent on the pinch-off voltages of the GaAsFETs used. These pinch-off voltages are again functions of ambient temperature, changing at the rate of -1 millivolt per .degree.C., and are further subject to process induced variations of up to 600 millivolts.
An input circuit for Capacitively Coupled Logic (CCL) is disclosed in the "IEEE Journal of Solid State Circuits," Vol. SC-18, No. 3, June 1983, page 359. The amplifier uses a pair of GaAsFETs in a nominally differential configuration. Both of the inputs, however, are capacitively coupled by back-biased diodes. The text of the article indicates that one of the inputs can be used as a reference node tied to the drain voltage supply. The use of a DC voltage on a capacitively coupled input node, as taught by this article, causes one of the inputs of the nominally differential pair to float. The differential feature is thus disabled and the circuit operates as a single-ended amplifier. Furthermore, if the circuit were modified to enable differential operation, the outputs would not switch symmetrically about a center, common mode voltage. The absence of a symmetrical output swing, however, does not affect operation of the circuit, as described, because only a single output is used.
An input level translator circuit is also discussed in the "IEEE Technical Digest" from the 1984 GaAs IC Symposium, page 11. An external temperature compensation circuit designed for use with the translator circuit is shown in "Applications Brief 1: Power Supply Requirements for Giga-Bit's 10G Picobit Logic Family".
The GigaBit level translator is built about an inverting GaAsFET stage. The circuit's switching threshold voltage is set by the ratio of the inverting GaAsFET's gate width to the gate width of a pull-up GaAsFET. The input ECL signal is voltage shifted to be centered about the circuit's switching threshold.
The level shifting of the ECL input signal down to the circuit's switching threshold is effected by a string of series diodes between the ECL input and the gate of the inverting GaAsFET. The voltage drop provided by this series diode string may be varied slightly by varying the forward current passing through the diodes. This forward current is varied by changing a tri voltage that biases the diodes. The trim voltage is provided by a comparator circuit that compares an externally generated ECL reference voltage with an externally generated GaAs reference voltage.
The aforementioned Applications Brief indicates that the temperature compensation circuit is only effective over a 15.degree. C. temperature range. The circuit is not compensated for process variations in the widths of the inverting and pullup GaAsFET gates, nor is the circuit compensated for process variations in the voltage dropping diodes. Finally, the trim voltage that "tweaks" the level translating circuit is externally generated and may not have the same temperature or process characteristics as the ECL and GaAs circuits with which the translator is being used.
U.S. Pat. No. 4,616,189, issued Oct. 7, 1986, discloses the use of a feedback loop to stabilize the common mode operating point of a differential amplifier. As illustrated in simplified form in FIG. 1 of the patent, the differential amplifier comprises source-coupled input transistors QA and QB routing a load current from a current source IA through load transistors QC and QD in response to a differential input voltage signal VIN. A level shifting circuit 10 shifts the voltage between the drains of transistors QA and QB to provide a differential output voltage signal VOUT. The feedback loop includes a matching pair of resistors RA and RB connected in series across the level shifting circuit 10 output to provide a common mode voltage VCM. An additional source-coupled pair of transistors QE and QF is provided with the drain-source path of transistor QF being connected between current source IA and the sources of transistors QA and QB. The drain of transistor QE is grounded. The common mode voltage VCM is level shifted by another shifting circuit 12 to provide a control voltage VX at the gate of transistor QF. A reference voltage VREF is applied to the gate of transistor QE. If the common mode voltage VCM rises above a threshold level, control voltage VX rises and causes transistor QF to increase the load current flowing through transistors QA and QB. The increased load current increases the voltage developed across load transistors QC and QD, thereby lowering the common mode voltage VCM. Similarly, when the common mode voltage VCM falls below the threshold level, VX falls causing transistor QF to reduce load current flow through transistors QA and QB, and causing the common mode voltage VCM to rise back up toward the threshold level. Thus, the threshold level tends to remain at a stable operating point.
The circuit of FIG. 1, above, provides a phase and amplitude matched "true" common mode output signal. However, the feedback loop has some disadvantages. Insertion of transistor QF into the path of the load current requires an increase in the minimum supply voltage differential +V - (-V) needed for proper operation. Moreover, while the feedback loop improves common mode rejection when the frequency of the common mode input signal is low, when high common mode frequencies are present in the input signal, feedback becomes positive due to increased signal delay in the loop and causes the amplifier circuit to become unstable. Also, while the feedback loop provides good control over the common mode operating point at lower frequencies, the amplifier circuit does not necessarily permit the common mode operating point to track variations in input threshold level of a logic circuit that the amplifier may be driving. Such variation may occur as a result of temperature or process variations.